module wdt_tb;
  reg clk, rst, clkwdt;
  wire bark,flag;
  wire [4:0]cnt;

  wdt dut(
    .clk(clk),
    .rst(rst),
    .clkwdt(clkwdt),
    .bark(bark),
    .flag(flag),
    .cnt(cnt)
  );

  initial begin
    clk = 0;
    rst = 0;
    clkwdt = 0;
    #10 rst = 1;
  end

  initial begin
    clk = 0;
    repeat (6) begin
    #30 clk = ~clk;
    end
  end
  
  initial begin
    clkwdt = 0;
    repeat (180) begin
    #1 clkwdt = ~clkwdt;
    end
  end

  initial begin
    $dumpfile("wdtwave.vcd");
    $dumpvars(0,wdt_tb);
  end


endmodule
  
  
